1. Field of the Invention
The present invention relates to a semiconductor memory device fabrication method, more particularly to a method of fabricating bitlines for a semiconductor memory device.
2. Background of the Related Art
Related art DRAM structures include a bitline lower portion structure using an Elevated Silicon Layer (ESL), a bitline lower portion structure using a Poly Plug, and a Self Aligned Contact structure. The bitline structures using the Elevated Silicon Layer and the Poly Plug have bitline contacts.
Three related art structures will now be described. First, a Silicon Epitaxial Growing Type of the Elevated Silicon Layer structure (ESL) will be described. The process for forming bitline lower portion structure of Epitaxial Growing Type in a related art DRAM fabrication is shown in FIG. 1A to FIG. 1D.
As shown in FIG. 1A, in order to manufacture a transistor, an isolation process is performed on a silicon substrate 1 to form an active region 2 and a field region 3. After the isolation process is performed, a gate oxide film 4 is formed on the silicon substrate 1, and then a wordline is formed thereon.
In order to form the wordline, polysilicon 5, wordline conductor 6 and wordline insulator 7 are sequentially deposited, and then a photolithography process is performed on the wordline insulator 7 to provide a photoresist pattern. Using the photoresist pattern as a mask, the wordline insulator 7, the wordline conductor 6, the polysilicon 5 and the gate oxide film 4 are etched to form a wordline 10.
As shown in FIG. 1B, when a photolithography process and an etching process are performed after an insulation film 8 has been deposited, insulation sidewall spacers 9 are formed on sidewalls of the wordlines by a reactive ion etching process that etches only a portion of the insulation film 8 corresponding to the active region 2. As shown in FIG. 1C, a silicon layer 11 is grown only on an exposed portion of the active region 2. The silicon layer 2 grown in this manner is referred to as an Elevated Silicon Layer.
After an insulation film has been deposited, a chemical mechanical polishing process is performed on the exposed entire surface so the exposed surface is planarized, and then, an interlayer dielectric film 12 is deposited on the planarized entire surface. The chemical mechanical polishing process is performed until the entire surface of the wordline is exposed. Subsequently, a contact photolithography process and an etching process are sequentially performed on the interlayer dielectric film 12 so that a contact 13 for connecting the grown silicon layer 11 and a bitline is made on the active region 2.
As shown in FIG. 1D, a bitline barrier 14, a bitline conductor 15, and a bitline insulation film 16 are sequentially formed on entire surface of the interlayer dielectric film 12 including the contact 13.
As shown in FIG. 2A to FIG. 2D, the process for forming a bitline lower portion structure of polysilicon plug type in a related art DRAM fabrication will now be described. As shown in FIG. 2A, to make a transistor, an isolation process is performed on a silicon substrate 21 so that the surface of the silicon substrate 21 is divided into an active region 22 and a field region 23.
After the isolation process has been performed, a gate oxide film 24 is grown on the silicon substrate 21, and then wordlines 28 are formed on the gate oxide film 24. As shown in FIG. 2a, each of the wordlines includes a first conductor 25, a second conductor 26 and a wordline insulation film 27 on its upper surface.
As shown in FIG. 2B, an insulation film is deposited on an exposed entire surface including the wordlines 28, and then insulation sidewall spacers 29 are formed on sidewalls of the wordlines 28 by a reactive ion etching process. A silicon layer 30 is deposited on the substrate 21 exposed between the wordlines 28 corresponding to the active region 22. To expose the active region corresponding to a source region and to a drain region, a photolithography process and an etching process are sequentially performed (not shown).
As shown in FIG. 2C, an insulation film (not shown) is deposited on an entire surface including the wordlines 28 and the silicon layer 30. Thereafter, the exposed entire surface is planarized by a chemical mechanical polishing process.
An interlayer dielectric film 31 is then deposited on the planarized entire surface. A photolithography process and an etching process for a bitline contact are sequentially performed (not shown) so that a bitline contact 32 is formed on the interlayer dielectric film 31.
As shown in FIG. 2D, a bitline barrier 33, a bitline material 34, and a bitline insulation film 35 are sequentially deposited on the interlayer dielectric film 31 including the bitline contact 32. Thereafter, a photolithography process and an etching process are sequentially performed to complete a bitline 36.
As shown in FIG. 3A to FIG. 3B, the process for forming bitline structure of a self aligned contact type in a related art DRAM fabrication will now be described. As illustrated in FIG. 3A, to make a transistor, an active. region 42 and a field region 43 are identified on a silicon substrate 41 by an isolation process. After the isolation process has been performed, a gate oxide layer 44 is grown on the entire silicon substrate 41 and then wordlines 45 are formed on the oxide film 44. Each wordline 45 includes a first conductor 46, a second conductor 47 and a wordline insulation film 48.
Referring to FIG. 3B, an insulation film 50 is deposited on the wordlines 45 and on the exposed portion of the silicon substrate 41. Insulation sidewall spacers 49 are formed on sidewalls of the wordlines 45 by a reactive ion etching process.
Subsequently, after an interlayer dielectric film 50 has been deposited on the exposed entire surface, a photolithography process and an etching process are sequentially performed on the interlayer dielectric film 50 so that contacts (51) for sources and drains are formed. The interlayer dielectric layer 50 is etched by using an etching selectivity ratio for the interlayer dielectric film 50 deposited on the insulation sidewall spacer 49 different from an etching selectivity ratio for the insulation sidewall spacer 49.
Thereafter, a silicon layer is deposited in the contacts 51 for a source and a drain, and then a chemical mechanical polishing process is performed for planarizing (not illustrated) the resultant surface of the silicon layer. A bitline is formed by depositing a bitline barrier material and a bitline material in sequence.
As described above, the related art processes have various disadvantages. According to the related art processes, after a lower portion structure of a bitline has first been fabricated, then bitline contacts are fabricated. Therefore, the bitlines are connected with the source region and the drain region through the contacts. However, when DRAM is substantially fabricated, forming a contact for the bitline in each cell is a very difficult process. Furthermore, an essential photolithography process among the various processes being used for forming contacts of memory cell is getting more and more difficult as the line width for the alignment of the contacts with the lower layer is smaller.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a semiconductor memory device fabrication method simplifying a process for fabricating the semiconductor memory device.
Another object of the present invention to provide a semiconductor memory device fabrication method that forms bitlines in the cell array.
Another object of the present invention to provide a semiconductor memory device fabrication method that can increase integration of the memory device.
Another object of the present invention to provide a semiconductor memory device fabrication method that directly forms bitlines coupled to wordlines of the device.
Another object of the present invention to provide a semiconductor memory device fabrication method omitting a process for forming contacts of bitlines in a cell array region.
To achieve at least the above objects and other advantages in a whole or in part and in accordance with purposes of the present invention, as embodied and broadly described, a method for fabricating a semiconductor memory device according to the present invention includes defining a cell array region and a peripheral circuitry region by forming a field region on a surface of a semiconductor substrate; forming a plurality of wordlines at predetermined interval in the cell array region and filling the regions demarcated by the predetermined interval with a semiconductor material to make a source region, a drain region and contacts between bit lines and capacitors; planarizing the entire resultant surfaces exposed in the cell array region and the peripheral circuitry region; directly forming bitlines without forming bitline contacts on the planarized surfaces; and forming insulation sidewall spacers on sidewalls of the bitlines so that the bitlines are insulated from each other.
To further achieve the above objects in a whole or in part, in accordance with the present invention, when a lower portion structure and an upper portion structure of a bitline of a semiconductor memory device are formed, a self aligned contact method is first used and then an elevated silicon layer is used to form the lower portion structure of the bitline.
To further achieve the above objects in a whole or in part, in accordance with the present invention, after a lower portion of the bitline of a semiconductor memory device is formed without forming the contact of the bitline, an upper portion structure can be formed on the lower portion structure of the bitline using various methods and structures.
In a first type of an upper portion structure, polysilicon is first deposited and then unnecessary portions of the polysilicon are removed. An insulation material is deposited and a chemical mechanical polishing process is performed thereon. A polysilicon plug is preferably formed by this process.
In a second type of an upper portion structure, an insulation material layer is first deposited and then unnecessary portions of the insulation material layer are removed. Polysilicon is deposited and a chemical mechanical polishing process is performed thereon. A capacitor node can be formed by this process.
In a third type of an upper portion structure, an insulation material layer is first deposited and then unnecessary portions of the insulation material layer are removed. Polysilicon is deposited and a chemical mechanical polishing process is performed. A resultant surface is planarized by this process.
In a fourth type of an upper portion structure, an oxide film is first deposited, and then unnecessary portions of the oxide film are removed. Subsequently, a lower electrode and a polysilicon layer are deposited and a chemical mechanical polishing process is performed. This process is to planarize the resultant surface and to separate a lower electrode from an upper electrode to be formed. Subsequently, an insulation layer is formed and then upper electrode is formed thereon.
To further achieve the above objects in a whole or in part, in accordance with the present invention, there is provided a method of fabricating a semiconductor memory device, the method including forming a plurality of wordlines extending along a first direction at a prescribed interval in a cell array region of a semiconductor substrate, filling regions demarcated by the prescribed interval with a semiconductor material to make source regions, drain regions and contact regions capable of connection with capacitors and bitlines, forming the bitlines to cross the wordlines in the cell array region without forming bitline contacts and forming insulation sidewall spacers on sidewalls of the bitlines to insulate the bitlines from each other.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.